The present invention relates to field effect transistor (FET), and more particularly, to an FET and method of manufacturing same from nanosheets.
The FET is a transistor used for amplifying or switching electronic signals. The FET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the FET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary FETs. The nFET uses electrons as the current carriers and with n-doped source and drain junctions. The pFET uses holes as the current carriers and with p-doped source and drain junctions.
FETs have been manufactured from nanosheets. A nanosheet is a structure having a diameter in the order of a nanometer. Nanowires promise to be the next device structure to allow device scaling. However, nanosheets are very difficult to manufacture due to their three-dimensional nature. While several solutions have been proposed, these solutions may include a number of drawbacks. For example, the proposed solutions may include a non-manufacturable process or the fabricated nanosheet may have a high parasitic capacitance.
Nanosheets of III-V semiconductor materials can be grown on Si (111) or other crystal orientation opening perpendicular to the seed opening. Therefore, it is desirable to grown III-V FET transistor structures using nanosheets.